1. Field of the Invention
The present invention relates to a structure of TEG wiring and a semiconductor substrate. More specifically, the present invention relates preferably to a structure of test element group (TEG) wiring that can be used in the analysis of the electrical characteristics and the like of semiconductor devices, and a semiconductor substrate that has such a structure of TEG wiring.
2. Background Art
With the high integration and miniaturization of semiconductor devices and the like in recent years, improvement of resolution in photolithography has been demanded. Resolution can be improved by enlarging the numerical aperture of the lens, or by shortening the wavelength of the exposure light. Therefore, the wavelength of exposure light has been shortened. For example, in the 65-nm node an ArF excimer laser is widely used as exposure light. The use of exposure light having a still shorter wavelength, such as F2 excimer laser light having a wavelength of 157.6 nm, has also been examined.
In order to further improve resolution, the method for elevating coherence using off-axis illumination or the like has been frequently used. In this case, however, the problems of the optical proximity effect such as corner rounding wherein a right-angle pattern is rounded, line shortening wherein a line pattern is shortened, line narrowing, and line widening will be significant.
Therefore, as a method for suppressing the optical proximity effect to faithfully transfer the pattern, OPC (optical proximity correction) is essential. In OPC, a method for eliminating pattern density difference, for example, by previously forming a wide mask pattern (bias type) or adding dummy patterns on the circumference of the pattern (feature type) is adopted to cope with pattern narrowing related to pattern density difference. Various OPC methods, such as forming the lines of the mask pattern to be long (extension type or hammer head type) as the countermeasure to line shortening, and adjusting the shape of the pattern-corner portions (outer serif or inner serif) as a countermeasure to corner rounding are also adopted.
However, as patterns are miniaturized or the wiring layout is diversified, the occurrence mode of the optical proximity effect has become complicated. Therefore, more complicated OPC has been required and the necessity for dealing with each pattern, such as the adjustment of the shape of each pattern using simulation model of lithography has increased. However, if OPC dealing with each pattern is used, the long processing time is required. Therefore, in the present stage, a method wherein accurate adjustment using simulation model or the like is performed when the offset value of a significant segment or a significant line is calculated, and the above-described so-called rule-base OPC regularized to some extent is performed for other portions. Therefore, the rule-base OPC is still frequently used.
On the other hand, in addition to the optical proximity effect, the flare of the light causes a problem of the inaccuracy pattern shape in fine exposure. Flare is caused by the scattered light reflected from the fine irregularity of the lens in the exposure apparatus or from the surface of a wafer, and deteriorates the contrast of exposure light. The contrast of exposure light plays an important role in pattern formation, and the deterioration of the contrast causes the problem of inaccuracy of the pattern shape and lowering of the exposure margin. As a measure to suppress flare, the use of a photomask having a flare-correcting region or the like has been proposed.
For defect analysis of semiconductor devices, the OBIRCH method using a TEG (test element group) wiring is frequently used. The OBIRCH method is a method wherein laser beams in the infrared region are radiated onto a wiring, and the defective wiring portion is identified from difference in the wiring resistance rising rate. However, since infrared beams are used in this analysis, point resolution is low. In the present stage, it is considered to be difficult to obtain specifically the resolution of about 3 μm or more. In other words, the analysis of a defect on the current path is difficult unless a space of at least about 3 μm or more exists. Therefore, the TEG wiring used in the OBIRCH method is an isolated wiring having a space between wirings of about 3 μm or more.
However, as miniaturization proceeds, the analysis of a defective fine pattern is required in the defect analysis. Specifically, defect analysis effective to a pattern having a space between wirings of a fine pitch of about 3 μm or less is required. Not only the analysis of such an isolated wiring pattern having a wiring interval of about 3 μm, but also the analysis of dense fine wiring patterns is required.
Furthermore, a wiring layout having a large rate of wiring and a wiring layout having a small rate of wiring are generally present in a mask. As the wiring structure is miniaturized, the variation of the wiring rate increases. It has been known that difference in wiring rate in a mask causes the flare effect, and this is difficult to deal with using only the shape correction of the above-described OPC or the like. Therefore, the data ratio on a mask must be averaged.